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KAD2708C
8-Bit, 275MSPS Analog-to-Digital Converter
Description
The Kenet KAD2708C is the industry's lowest power, 8-bit, high performance Analog-to-Digital converter. The converter runs at sampling rates up to 275MSPS, and is fabricated with Kenet's proprietary FemtoCharge(R) CMOS technology. Users can now obtain industry-leading SNR and SFDR specifications while nearly halving power consumption. Sampling rates of 210, 170 and 105MSPS are also available in the same pin-compatible package and in versions with 10-bit resolution. Kenet's KAD2708L offers this performance with LVDS outputs. All are available in 68-pin RoHS-compliant QFN packages with exposed paddle. Performance is specified over the full industrial temperature range (-40 to +85C).
Key Specifications
* * * SNR of 48.8dB at Nyquist SFDR of 68dBc at Nyquist Power consumption 265mW at fS = 275MSPS
Features
* * * * * * * * On-chip reference Internal track and hold 1.5VPP differential input voltage 600MHz analog input bandwidth Two's complement or binary output Over-range indicator Selectable /2 Clock Input LVCMOS compatible outputs Resolution, Speed 8 Bits 350MSPS 10 Bits 275MSPS 8 Bits 275MSPS 10 Bits 210MSPS 8 Bits 210MSPS 10 Bits 170MSPS 8 Bits 170MSPS 10 Bits 105MSPS 8 Bits 105MSPS LVDS Outputs KAD2708L-35 KAD2710L-27 KAD2708L-27 KAD2710L-21 KAD2708L-21 KAD2710L-17 KAD2708L-17 KAD2710L-10 KAD2708L-10 KAD2710C-27 KAD2708C-27 KAD2710C-21 KAD2708C-21 KAD2710C-17 KAD2708C-17 KAD2710C-10 KAD2708C-10 LVCMOS Outputs
Applications
* * * * * * * * * High-Performance Data Acquisition Portable Oscilloscope Medical Imaging Cable Head Ends Power-Amplifier Linearization Radar and Satellite Antenna Array Processing Broadband Communications Local Multipoint Distribution System (LMDS) Communications Test Equipment
Table 1. Pin-Compatible Products
300 Unicorn Park Dr., Woburn, MA 01801 Sales: 1-781-497-0060 FemtoCharge is a registered trademark of Kenet, Inc. Rev 1.1
Sales@kenetinc.com Copyright (c) 2007, Kenet, Inc. Page 1 of 17
KAD2708C 8-Bit, 275MSPS Analog-to-Digital Converter
Absolute Maximum Ratings1
Parameter AVDD2 to AVSS AVDD3 to AVSS OVDD2 to OVSS Analog Inputs to AVSS Clock Inputs to AVSS Logic Inputs to AVSS (VREFSEL, CLKDIV) Logic Inputs to OVSS (RST, 2SC) VREF TO AVSS Analog Output Currents Logic Output Currents CMOS Output Currents Operating Temperature Storage Temperature Junction Temperature -40 -65 Min -0.4 -0.4 -0.4 -0.4 -0.4 -0.4 -0.4 -0.4 Max 2.1 3.7 2.1 AVDD3 + 0.3 AVDD2 + 0.3 AVDD3 + 0.3 OVDD2 + 0.3 AVDD3 + 0.3 10 10 20 85 150 150 Unit V V V V V V V V mA mA mA C C C
1. Exposing the device to levels in excess of the maximum ratings may cause permanent damage. Exposure to maximum conditions for extended periods may affect device reliability.
Thermal Impedance
Parameter Junction to Paddle2 2. Paddle soldered to ground plane. Symbol JP Typ 30 Unit C/W
ESD
Electrostatic charge accumulates on humans, tools and equipment, and may discharge through any metallic package contacts (pins, balls, exposed paddle, etc.) of an integrated circuit. Industry-standard protection techniques have been utilized in the design of this product. However, reasonable care must be taken in the storage and handling of ESD sensitive products. Contact Kenet for the specific ESD sensitivity rating of this product.
Rev 1.1
Page 2 of 17
KAD2708C 8-Bit, 275MSPS Analog-to-Digital Converter
Electrical Specifications
All specifications apply under the following conditions unless otherwise noted: AVDD2 = 1.8V, AVDD3 = 3.3V, OVDD = 1.8V. TA = -40C to +85C, Typ values at 25C. fSAMPLE = 275MSPS fIN = Nyquist.
DC Specifications
Parameter Power Requirements 1.8V Analog Supply Voltage 3.3V Analog Supply Voltage 1.8V Output Supply Voltage 1.8V Analog Supply Current 3.3V Analog Supply Current 1.8V Output Supply Current Power Dissipation AVDD2 AVDD3 OVDD IAVDD2 IAVDD3 IOVDD PD 1.7 3.15 1.7 1.8 3.3 1.8 44 41 26 261 1.9 3.45 1.9 V V V mA mA mA mW Symbol Conditions Min Typ Max Units
Rev 1.1
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KAD2708C 8-Bit, 275MSPS Analog-to-Digital Converter
Analog Specifications
Parameter Analog Input Full-Scale Differential Analog Input Voltage Gain Temperature Coefficient Full Power Bandwidth Clock Input Sampling Clock Frequency Range CLKP, CLKN P-P Differential Input Voltage CLKP, CLKN Differential Input Resistance CLKP, CLKN Common-Mode Input Voltage Reference Internal Reference Voltage Reference Voltage Temperature Coefficient Common-Mode Output Voltage VREF VRTC VCM Full Temp 1.18 1.21 38 0.86 1.24 V ppm/C V fSAMPLE VCDI RCDI VCCI 50 0.5 10 0.9 275 1.8 MHz VPP M V VIN AVTC FPBW Full Temp 1.4 1.5 90 600 1.6 VPP ppm/C MHz Symbol Conditions Min Typ Max Units
AC Specifications
Parameter Signal to Noise Ratio Signal to Noise and Distortion Effective Number of Bits Spurious Free Dynamic Range Two-Tone SFDR Integral Nonlinearity Differential Nonlinearity Power Supply Rejection Ratio Word Error Rate Symbol SNR SINAD ENOB SFDR 2TSFDR INL DNL PSRR WER Conditions Full Temp Full Temp Full Temp Full Temp f1=133MHz, f2=135MHz -0.8 -0.3 42 Min 45.8 45.7 7.3 63 Typ 48.8 48.7 7.8 68 67 0.2 0.2 66 1x10-12 0.8 0.4 Max Units dB dB Bits dBc dBc LSB LSB dB
Rev 1.1
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KAD2708C 8-Bit, 275MSPS Analog-to-Digital Converter
Digital Specifications
Parameter Inputs High Input Voltage (VREFSEL) Low Input Voltage (VREFSEL) Input Current High (VREFSEL) Input Current Low (VREFSEL) High Input Voltage (CLKDIV) Low Input Voltage (CLKDIV) Input Current High (CLKDIV) Input Current Low (CLKDIV) High Input Voltage (RST,2SC) Low Input Voltage (RST,2SC) Input Current High (RST,2SC) Input Current Low (RST,2SC) Input Capacitance CMOS Outputs Voltage Output High Voltage Output Low Output Rise Time Output Fall Time VOH VOL tR tF 1.8 0 1.8 1.4 V V ns ns VREFSEL VIH VREFSEL VIL VREFSEL IIH VREFSEL IIL CLKDIV VIH CLKDIV VIL CLKDIV IIH CLKDIV IIL RST,2SC VIH RST,2SC VIL RST,2SC IIH RST,2SC IIL CDI VIN = OVDD VIN = OVSS 0 25 1 50 3 VIN = AVDD3 VIN = AVSS 25 0 0.8*OVDD2 0.2*OVDD2 10 75 65 1 VIN = AVDD3 VIN = AVSS 0 25 0.8*AVDD3 0.2*AVDD3 75 10 1 65 0.8*AVDD3 0.2*AVDD3 10 75 V V A A V V A A V V A A pF Symbol Conditions Min Typ Max Units
Rev 1.1
Page 5 of 17
KAD2708C 8-Bit, 275MSPS Analog-to-Digital Converter
Timing Diagram
Figure 1. LVCMOS Timing Diagram
Timing Specifications
Parameter Aperture Delay RMS Aperture Jitter Input Clock to Data Propagation Delay Input Clock to Output Clock Propagation Delay Output Clock to Data Propagation Delay Output Data to Output Clock Setup Time Output Clock to Output Data Hold Time Latency (Pipeline Delay) Over Voltage Recovery Symbol tA jA tPD tCPD tDC tSU tH L tOVR Min Typ 1.7 200 1.8 1.3 470 3 75 28 1 Max Units ns fs ns ns ps ns ps cycles cycle
Rev 1.1
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KAD2708C 8-Bit, 275MSPS Analog-to-Digital Converter
Pin Descriptions
Pin #
1, 14, 18, 20 2, 7, 10, 19, 21, 24 3 4 5 6, 15, 16, 25 8, 9 11-13, 29-36, 37, 39, 42, 46, 48, 50, 53, 54, 56, 58, 62, 63, 67 17 22, 23 26, 45, 61 27, 41, 44, 60 28 38 40 43 47 49 51 53 55 57 59 64-66 68 Exposed Paddle 2SC AVSS CLKDIV CLKN, CLKP OVSS OVDD2 RST D0 D1 CLKOUT D2 D3 D4 D5 D6 D7 OR Clock Divide by Two (Active Low) Clock Input Complement, True Output Supply Return 1.8V CMOS Supply Power On Reset (Active Low) LVCMOS Bit 0 (LSB) Output LVCMOS Bit 1 Output LVCMOS Clock Output LVCMOS Bit 2 Output LVCMOS Bit 3 Output LVCMOS Bit 4 Output LVCMOS Bit 5 Output LVCMOS Bit 6 Output LVCMOS Bit 7 Output Over Range Connect to OVDD2 Two's Complement Select (Active Low) Analog Supply Return
Name
AVDD2 AVSS VREF VREFSEL VCM AVDD3 INP, INN DNC
Function
1.8V Analog Supply Analog Supply Return Reference Voltage Out/In Reference Voltage Select (0:Int 1:Ext) Common Mode Voltage Output 3.3V Analog Supply Analog Input Positive, Negative Do Not Connect
Rev 1.1
Page 7 of 17
KAD2708C 8-Bit, 275MSPS Analog-to-Digital Converter
Pin Configuration
68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
2SC DNC OVDD2 OVDD2 OVDD2 DNC DNC OVSS OVDD2 ORP DNC D7 DNC D6 DNC D5 DNC
AVDD2 AVSS VREF VREFSEL VCM AVDD3 AVSS INP INN AVSS DNC DNC DNC AVDD2 AVDD3 AVDD3 CLKDIV
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
68 QFN
51 50 49 48 47 46 45 44 43 42 41 40 39
D4 DNC D3 DNC D2 DNC OVSS OVDD2 CLKOUT DNC OVDD2 D1 DNC D0 DNC DNC DNC
Top View Not to Scale
38 37 36 35
Rev 1.1
AVDD2 AVSS AVDD2 AVSS CLKN CLKP AVSS AVDD3 OVSS OVDD2 RST DNC DNC DNC DNC DNC DNC
Figure 2. Pin Configuration
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
Page 8 of 17
KAD2708C 8-Bit, 275MSPS Analog-to-Digital Converter
Typical Operating Characteristics
AVDD3=3.3V, AVDD2=OVDD2 =1.8V, TAMBIENT (TA)=25C, fSAMPLE=275MHz, VIN=6.865MHz @ -0.5dBFS unless noted.
50 45 40 35 30 25 20 15 -30
SFDR (dB) 75 70 65 60 55 50 45 40 35 30 25 -30
SNR (dB)
-25
-20
-15
-10
-5
0
-25
-20
-15
-10
-5
0
Analog Input Amplitude (dBFS)
Input Amplitude (dBFS)
Figure 3. SNR vs. Vin
280 260 240 220 200 180 160 140 120 100 50
Figure 4. SFDR vs. Vin
-30 HD2, HD3 dBc -40 -50 -60 -70 -80 -30
HD2 HD3
-25
-20
-15
-10
-5
0
Power Dissipation (PD) (mW)
100
Input Amplitude (dBFS)
150 200 f SAMPLE (f S ) (MHz)
250
300
Figure 5. HD2, 3 vs. Vin
50 -65 -70 -75 dBc 49 -80 48.5 -85 -90 50 75 100 125 150 175 200 225 250 275 300 f SAMPLE (MHz) 50
Figure 6. Power Dissipation vs. fSAMPLE
49.5 SNR (dB)
HD3
HD2
48
75
100 125 150 175 200 225 250 275 300 f SAMPLE (MHz)
Figure 7. SNR vs. fSAMPLE Rev 1.1
Figure 8. HD2, 3 vs. fSAMPLE Page 9 of 17
KAD2708C 8-Bit, 275MSPS Analog-to-Digital Converter
AVDD3=3.3V, AVDD2=OVDD2 =1.8V, TAMBIENT (TA)=25C, fSAMPLE=275MHz, VIN = 6.865MHz @ -0.5dBFS unless noted.
72 71 SFDR (dBc) 70 69 68 67 50 75 100 125 150 175 200 225 250 275 300 f SAMPLE (MHz)
0.25 0.2 0.15 0.1 DNL (LSBs) 0.05 0 -0.05 -0.1 -0.15 -0.2 -0.25 0 32 64 96 128 code 160 192 224 255
Figure 9. SFDR vs. fSAMPLE
0.25 0.2 0.15 0.1 INL (LSBs) 0.05 0 -0.05 -0.1 -0.15 -0.2 -0.25 0 32 64 96 128 code 160 192 224 255 Counts
Figure 10. Differential Nonlinearity vs. Output Code
50,000 45,000 40,000 35,000 30,000 25,000 20,000 15,000 10,000 5,000 0 126 127 128 129
code
Figure 11. Integral Nonlinearity vs. Output Code
0 -10 -20 -30 Amplitude (dB) -40 -50 -60 -70 -80 -90 -100 0 20 40 60 80 Frequency (MHz) 100 120 Vin = -0.25dBFS SNR = 49.2dB SFDR = 71.0dBc
Figure 12. Noise Histogram
0 -10 -20 -30 Amplitude (dB) -40 -50 -60 -70 -80 -90 -100 0 20 40 60 80 Frequency (MHz) 100 120 Vin = -0.22dBFS SNR = 49.0dB SFDR = 69.2dBc SINAD = 49.0dB HD2 = -77dBc HD3 = -69dBc
SINAD = 49.0dB HD2 = -83dBc HD3 = -66dBc
Figure 13. Output Spectrum at 6.865MHz Rev 1.1
Figure 14. Output Spectrum at 68.465MHz Page 10 of 17
KAD2708C 8-Bit, 275MSPS Analog-to-Digital Converter
AVDD3=3.3V, AVDD2=OVDD2 =1.8V, TAMBIENT (TA)=25C, fSAMPLE=275MHz unless noted.
0 -10 -20 -30 Amplitude (dB) -40 -50 -60 -70 -80 -90 -100 0 20 40 60 80 Frequency (MHz) 100 120 Vin = -0.27 SNR = 49.1dB SFDR = 66.8dBc
Amplitude (dB) 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 0 20 40 60 80 Frequency (MHz) 100 120 Vin = -0.26dBFS SNR = 49.1dB SFDR = 70.3dBc SINAD = 48.9dB HD2 = -79dBc HD3 = -69dBc
SINAD = 48.8dB HD2 = -85dBc HD3 = -68dBc
Figure 15. Output Spectrum at 130.565MHz
0 -10 -20 -30 Amplitude (dB) -40 -50 -60 -70 -80 -90 -100 0 20 40 60 80 Frequency (MHz) 100 120 Vin = -0.25dBFS SNR = 48.5dB SFDR = 58.2dBc SINAD = 47.8dB HD2 = -58dBc HD3 = -61dBc
Figure 16. Output Spectrum at 143.155MHz
Figure 17. Output Spectrum at 492.965MHz
Rev 1.1
Page 11 of 17
KAD2708C 8-Bit, 275MSPS Analog-to-Digital Converter
Functional Description
The KAD2708 is based upon a eight bit, 275MSPS A/D converter in a pipelined architecture. The input voltage is captured by a sample & hold circuit and converted to a unit of charge. Proprietary charge domain techniques are used to compare the input to a series of reference charges. These comparisons determine the digital code for each input value. The converter pipeline requires 24 sample clocks to produce a result. Digital error correction is also applied, resulting in a total latency of 28 clock cycles. This is evident to the user as a latency between the start of a conversion and the data being available on the digital outputs. At start-up, a self-calibration is performed to minimize gain and offset errors. The reset pin (RST) is initially held low internally at power-up and will remain in that state until the calibration is complete. The clock frequency should remain fixed during this time. Calibration accuracy is maintained for the sample rate at which it is performed, and therefore should be repeated if the clock frequency is changed by more than 10%. Recalibration can be initiated via the RST pin, or power cycling, at any time. the system. Additionally, an externally provided reference can be changed from the nominal value to adjust the full-scale input voltage within a limited range. To select whether the full-scale reference is internally generated or externally provided, the digital input port VREFSEL should be set appropriately, low for internal or high for external. This pin also has an internal 18k pull-up resistor. To use the internally generated reference VREFSEL can be tied directly to AVSS, and to use an external reference VREFSEL can be allowed to float.
Analog Input
The fully differential ADC input (INP/INN) connects to the sample and hold circuit. The ideal full-scale input voltage is 1.5VPP, centered at the VCM voltage of 0.86V as shown in Figure 18.
Reset
The KAD2708C resets and calibrates automatically on power-up. To force a reset and initiate recalibration of the ADC after power-up, connect an open-drain output device to drive pin 28 (RST) and pull low for at least ten sample clock periods. Do not use a device with a pull-up on the reset pin, as it may prevent the KAD2708 from properly executing the power-on reset.
Figure 18. Analog Input Range Best performance is obtained when the analog inputs are driven differentially in an ac-coupled configuration. The common mode output voltage, VCM, should be used to properly bias each input as shown in Figures 19 and 20. An RF transformer will give the best noise and distortion performance for wideband and/or high intermediate frequency (IF) inputs. The recommended biasing is shown in Figure 19.
Voltage Reference
The VREF pin is the full-scale reference, which sets the full-scale input voltage for the chip and requires a bypass capacitor of 0.1uF or larger. An internally generated reference voltage is provided from a bandgap voltage buffer. This buffer can sink or source up to 50A externally. An external voltage may be applied to this pin to provide a more accurate reference than the internally generated bandgap voltage or to match the full-scale reference among a system of KAD2708C chips. One option in the latter configuration is to use one KAD2708C's internally generated reference as the external reference voltage for the other chips in Rev 1.1
Figure 19. Transformer Input Page 12 of 17
KAD2708C 8-Bit, 275MSPS Analog-to-Digital Converter
The value of the termination resistor should be determined based on the desired impedance. The differential input impedance of the KAD2708 is 10M. A differential amplifier can be used in applications that require dc coupling, at the expense of reduced dynamic performance. In this configuration the amplifier will typically reduce the achievable SNR and distortion performance. A typical differential amplifier configuration is shown in Figure 20. rate, then use the KAD2708C's divide-by-2 to generate a 50%-duty-cycle clock. The divider only uses the rising edge of the clock, so 50% clock duty cycle is assured . CLKDIV Pin
AVSS AVDD
Divide Ratio
2 1
Table 3. CLKDIV Pin Settings
Jitter
In a sampled data system, clock jitter directly impacts the achievable SNR performance. The theoretical relationship between clock jitter and maximum SNR is shown in Equation 1 and is illustrated in Figure 22.
Figure 20. Differential Amplifier Input
1 SNR = 20 log 10 2 f t IN J
Where tj is the RMS uncertainty in the sampling instant.
Clock Input
The clock input circuit is a differential pair (see Figure 24). Driving these inputs with a high level (up to 1.8VPP on each input) sine or square wave will provide the lowest jitter performance. The recommended drive circuit is shown in Figure 21. The clock inputs can be driven single-ended, but this is not recommended as performance will suffer.
Equation 1. This relationship shows the SNR that would be achieved if clock jitter were the only non-ideal factor. In reality, achievable SNR is limited by internal factors such as differential nonlinearity, aperture jitter and thermal noise.
100 95 90 85 tj=0.1ps 14 Bits
SNR - dB
80 75 70 65 60 55 tj=100ps tj=10ps
tj=1ps
12 Bits
10 Bits
Figure 21. Recommended Clock drive The CLKDIV pin is a 1.8V CMOS control pin (input) that selects whether the input clock frequency is passed directly to the ADC or divided by two. Applying a low level will divide by two; 1.8V applied (or left floating) will not divide. Use of the clock divider is optional. The KAD2708C's ADC requires a clock with 50% duty cycle for optimum performance. If such a clock is not available, one option is to generate twice the desired sampling Rev 1.1
50 1 10 100 1000
Input Frequency - MHz
Figure 22. SNR vs. Clock Jitter Any internal aperture jitter combines with the input clock jitter, in a root-sum-square fashion since they are not statistically correlated, and this determines the total jitter in the system. The total jitter, combined with other noise sources, then determines the achievable SNR. Page 13 of 17
KAD2708C 8-Bit, 275MSPS Analog-to-Digital Converter
Equivalent Circuits Layout Considerations
Split Ground and Power Planes
Data converters operating at high sampling frequencies require extra care in PC board layout. Many complex board designs benefit from isolating the analog and digital sections. Analog supply and ground planes should be laid out under signal and clock inputs. Locate the digital planes under outputs and logic pins. Grounds should be joined under the chip.
Figure 23. Analog Inputs
Clock Input Considerations
Use matched transmission lines to the inputs for the analog input and clock signals. Locate transformers, drivers and terminations as close to the chip as possible.
Bypass and Filtering
Bulk capacitors should have low equivalent series resistance. Tantalum is a good choice. For best performance, keep ceramic bypass capacitors very close to device pins. Longer traces will increase inductance, resulting in diminished dynamic performance and accuracy. Make sure that connections to ground are direct and low impedance. Avoid forming ground loops.
LVCMOS Outputs
Output traces and connections must be designed for 50 characteristic impedance. Figure 24. Clock Inputs
Unused Inputs
Three of the four standard logic inputs (RESET, CLKDIV, 2SC) which will not be operated do not require connection for best ADC performance. These inputs can be left open if they are not used. VREFSEL must be held low for internal reference, but can be left open for external reference.
Figure 25. LVCMOS Outputs
Rev 1.1
Page 14 of 17
KAD2708C 8-Bit, 275MSPS Analog-to-Digital Converter
Definitions
Analog Input Bandwidth is the analog input frequency at which the spectral output power at the fundamental frequency (as determined by FFT analysis) is reduced by 3dB from its full-scale low-frequency value. This is also referred to as Full Power Bandwidth. Aperture Delay or Sampling Delay is the time required after the rise of the clock input for the sampling switch to open, at which time the signal is held for conversion. Aperture Jitter is the RMS variation in aperture delay for a set of samples. Clock Duty Cycle is the ratio of the time the clock wave is at logic high to the total time of one clock period. Differential Non-Linearity (DNL) is the deviation of any code width from an ideal 1 LSB step. Effective Number of Bits (ENOB) is an alternate method of specifying Signal to Noise-and-Distortion Ratio (SINAD). In dB, it is calculated as: ENOB = (SINAD-1.76) / 6.02. Integral Non-Linearity (INL) is the deviation of each individual code from a line drawn from negative fullscale (1/2 LSB below the first code transition) through positive full-scale (1/2 LSB above the last code transition). The deviation of any given code from this line is measured from the center of that code. Least Significant Bit (LSB) is the bit that has the smallest value or weight in a digital word. Its value in terms of input voltage is VFS/(2N-1) where N is the resolution in bits. Missing Codes are output codes that are skipped and will never appear at the ADC output. These codes cannot be reached with any input value. Most Significant Bit (MSB) is the bit that has the largest value or weight. Its value in terms of input voltage is VFS/2. Pipeline Delay is the number of clock cycles between the initiation of a conversion and the appearance at the output pins of the corresponding data. Power Supply Rejection Ratio (PSRR) is the ratio of a change in power supply voltage to the input voltage necessary to negate the resultant change in output code. Signal to Noise-and-Distortion (SINAD) is the ratio of the RMS signal amplitude to the RMS value of the sum Rev 1.1 Page 15 of 17 of all other spectral components below one half the clock frequency, including harmonics but excluding DC. Signal-to-Noise Ratio (without Harmonics) is the ratio of the RMS signal amplitude to the sum of all other spectral components below one-half the sampling frequency, excluding harmonics and DC. Spurious-Free-Dynamic Range (SFDR) is the ratio of the RMS signal amplitude to the RMS value of the peak spurious spectral component. The peak spurious spectral component may or may not be a harmonic. Two-Tone SFDR is the ratio of the RMS value of either input tone to the RMS value of the peak spurious component. The peak spurious component may or may not be an IMD product.
KAD2708C 8-Bit, 275MSPS Analog-to-Digital Converter
Outline Dimensions
D D/2 D1 D1/2
PIN 1 ID 0.80 DIA E1/2 E/2
E1
E
TOP VIEW
CC
b
A1
e
TERMINAL TIP
SECTION "C-C" SCALE: NONE
A A1 4X P
b
D2 D2/2 4X P 0.45
E2
16Xe REF.
E2/2
0.25 MIN L 0.25 MIN SEATING PLANE 16Xe REF. BOTTOM VIEW
e
Rev 1.1
Page 16 of 17
KAD2708C 8-Bit, 275MSPS Analog-to-Digital Converter
Package Dimensions (mm)
Ref A A1 b D D1 D2 e E E1 E2 L N ND NE P 0 0 0.42 7.55 0.50 7.55 Min 0.00 0.18 Nom 0.90 0.01 0.23 10.00 BSC 9.75 BSC 7.70 0.50 BSC 10.00 BSC 9.75 BSC 7.70 0.60 68 17 17 12' 0.60 7.85 0.65 Total terminals Terminals in D (x) direction Terminals in E (y) direction 7.85 Max 1.00 0.05 0.30 Per JEDEC MO-220 Measured between 0.20 and 0.25mm from plated terminal tip Note
Ordering Guide
RoHS stances (RoHS). Contact Kenet for a materials declaration for this product.
This product is compliant with EU directive 2002/95/EC regarding the Restriction of Hazardous Sub-
Model
KAD2708C-27Q68 KAD2708C-21Q68 KAD2710C-17Q68 KAD2710C-10Q68
Speed
275MSPS 210MSPS 170MSPS 105MSPS
Package
68-QFN EP 68-QFN EP 68-QFN EP 68-QFN EP
Temp. Range
-40C to +85C -40C to +85C -40C to +85C -40C to +85C
Rev 1.1
Page 17 of 17

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